INTEL SILICON & SEMICONDUCTOR ENGINEERING
Skills to Put on Resume for Hardware Engineer at Intel
SystemVerilog, UVM, RTL Design, x86/RISC-V Architecture, PCIe, STA, Post-Silicon Validation & EDA Tools
Intel Engineering Focus:
Intel evaluates Hardware Engineers on microarchitecture design (RTL/SystemVerilog),
advanced functional verification (UVM, Formal Verification), physical design & static timing analysis (STA), high-speed
interconnect protocols (PCIe, CXL, DDR5), silicon bring-up, and EDA tool proficiency (Synopsys, Cadence).
1. TECHNICAL COMPETENCIES & SILICON ENGINEERING
Logic Design & Microarchitecture
HDLs & RTL:
SystemVerilog, Verilog, VHDL,
Chisel, Logic Synthesis, Clock Domain
Crossing (CDC), Linting.
Computer Architecture:
x86 Architecture,
RISC-V, ARM, Pipelining, Cache Coherency
(MESI/MOESI), Memory Controllers.
Interconnects & Bus Protocols:
PCIe (Gen
5/6), Compute Express Link (CXL), AMBA (AXI/
AHB/APB), UCIe, CNI, AMBA CHI.
Low-Power Design:
Power Gating, Clock
Gating, Multi-VDD, UPF/CPF, Dynamic Voltage
and Frequency Scaling (DVFS).
Verification, Validation & Emulation
Design Verification (DV):
UVM (Universal
Verification Methodology), SystemVerilog
Assertions (SVA), Functional Coverage.
Formal Verification:
JasperGold, VC Formal,
Property Specification Language (PSL),
Equivalence Checking (LEC).
Emulation & FPGA Prototyping:
Synopsys
ZeBu, Cadence Palladium, Intel Stratix/Agilex
FPGAs, Quartus Prime.
Post-Silicon Validation:
Silicon Bring-Up, Lab
Diagnostics, Logic Analyzers, Oscilloscopes,
JTAG, Python Test Automation.
Physical Design, STA & Fabrication
Physical Design & Synthesis:
Synopsys
Design Compiler, Fusion Compiler, Cadence
Genus, Floorplanning, Place & Route (P&R).
Static Timing Analysis (STA):
Synopsys
Primetime, Setup/Hold Timing Closure, Multi-
Corner Multi-Mode (MCMM).
Signal & Power Integrity (SI/PI):
Ansys
RedHawk, Apache Sentinel, S-Parameters, Eye
Diagram Analysis, Crosstalk, IR Drop.
Advanced Packaging:
Intel Foveros 3D
Stacking, EMIB (Embedded Multi-die
Interconnect Bridge), Chiplet Architecture.
Scripting, EDA Tooling & Methodologies
Scripting & Automation:
Python, Tcl, Perl,
Bash, C/C++ (SystemC, DPI-C).
EDA Toolsuits:
Synopsys (Design Compiler,
PrimeTime, VCS), Cadence (Innovus, Xcelium),
Siemens EDA (Questa, Tessent).
Design for Test (DFT):
Scan Insertion, ATPG
(Automatic Test Pattern Generation), MBIST,
Boundary Scan (IEEE 1149.1).
Methodologies:
Agile Hardware Development,
Git, Perforce, Bug Tracking (Jira), Technical
Documentation.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Hardware Engineer at Intel Resume Skills Blueprint
Page 1 of 2
